Formation of multi-level semiconductor devices entails the formation of multiple levels of metal interconnects such as vias and trench lines (local interconnect lines). For example, in a multi-level semiconductor device there are frequently formed uppermost metallization layers that include relatively wide metal areas, such as bonding pads having a linewidth and depth of about 1 micron to about 5 microns which are connected to lower lying metallization layers through relatively narrow metal filled holes, also referred to as vias. Frequently, several vias will connect a bonding pad in an uppermost metallization layer in one metallization level to an underlying metallization level through several relatively narrower vias. For example the underlying vias and metal interconnect lines are typically formed with line widths having a dimensions of from about 0.25 microns and smaller. The electrical continuity of the various metal interconnects, particularly through the vias is critical to proper functionality of a device.
Copper and copper alloys are increasingly becoming the metal of choice in forming damascene structures as it has improved electrical resistivity and electrical migration resistance compared to aluminum, previously widely used as a metallization metal. The use of copper, however, has presented several manufacturing problems that must be overcome for successful implementation of the technology. For example, copper cannot be successfully etched to form metal lines since it does not form volatile components with known etching chemistry's. As a result, copper lines must be formed as metal inlaid structures, also referred to as damascenes or dual damascenes where an anisotropically etched opening is formed in a dielectric insulating layer followed by filling the opening with copper and planarizing the wafer process surface by a chemical mechanical polishing step.
One damascene process that has been widely used for sub-micron metal linewidths, for example less than about 0.25 microns, is a dual damascene process whereby both an underlying via and an overlying metal interconnect line are simultaneously filled with copper. Prior art processes in forming the uppermost metallization layer, for example including bonding pads, have used a single damascene process to first form underlying vias and a single damascene process to form the overlying bonding pad. Some problems with the prior art process for forming bonding pads include the fact is that it is costly in terms of cycle time to first form a single damascene via and then a single damascene overlying bonding pad. A cycle time and material processing costs are increased by forming an intervening copper capping layer to protect the copper via from exposure to the atmosphere, which may tend to cause acidic corrosion due to residual sulfur compounds remaining from an electro-chemical plating process. Frequently, extensive cleaning and environmental storage processes must be undertaken to protect the top portions of the copper vias from such corrosive reactions, which tend to increase an electrical resistance and adversely affect overlying material layer adhesion.
There is therefore a need in the semiconductor manufacturing art for an improved method to form ultra-thick damascene copper features including bonding pads to avoid corrosive attack of underlying copper filled vias while reducing a cycle time and processing cost.
It is therefore an object of the invention to provide an improved method to form ultra-thick damascene copper features including bonding pads to avoid corrosive attack of underlying copper filled vias while reducing a cycle time and processing cost in addition to overcoming other deficiencies and shortcomings of the prior art.